By Daniel J. Sorin, Mark D. Hill, David A. Wood
Many smooth computers and such a lot multicore chips (chip multiprocessors) help shared reminiscence in undefined. In a shared reminiscence process, all of the processor cores may well learn and write to a unmarried shared tackle area. For a shared reminiscence laptop, the reminiscence consistency version defines the architecturally noticeable habit of its reminiscence method. Consistency definitions offer principles approximately lots and shops (or reminiscence reads and writes) and the way they act upon reminiscence. As a part of assisting a reminiscence consistency version, many machines additionally offer cache coherence protocols that make sure that a number of cached copies of information are stored updated. The aim of this primer is to supply readers with a uncomplicated figuring out of consistency and coherence. This figuring out comprises either the problems that needs to be solved in addition to a number of recommendations. We current either highlevel recommendations in addition to particular, concrete examples from real-world platforms. desk of Contents: Preface / advent to Consistency and Coherence / Coherence fundamentals / reminiscence Consistency Motivation and Sequential Consistency / overall shop Order and the x86 reminiscence version / secure reminiscence Consistency / Coherence Protocols / Snooping Coherence Protocols / listing Coherence Protocols / complex themes in Coherence / writer Biographies
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Additional info for A Primer on Memory Consistency and Cache Coherence
So long as the loads and stores are performed in program order, it does not matter in what order coherence permissions are obtained. Implementations may do non-binding prefetches without affecting the memory consistency model. , stream buffers) and more aggressive cores. , have their effects nullified) on a branch misprediction. These squashed loads and stores can be made to look like non-binding prefetches, enabling this speculation to be correct because it has no effect on SC. A load after a branch prediction can be presented to the L1 cache, wherein it either misses (causing a non-binding GetS prefetch) or hits and then returns a value to a register.
11). 1 (this example, as is the case for all examples in this chapter, assumes that the initial values of all variables are zero). Most programmers would expect that core C2’s register r2 should get the value NEW. Nevertheless, r2 can be 0 in some of today’s computer systems. Hardware can make r2 get the value 0 by reordering core C1’s stores S1 and S2. , if we look only at C1’s execution and do not consider interactions with other threads), this reordering seems correct because S1 and S2 access different addresses.
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