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By Alpha Architecture Committee, Richard T. Witek
This can be the authoritative reference on electronic apparatus Corporation's new 64-bit RISC Alpha structure. Written through the designers of the interior electronic requirements, this publication includes whole descriptions of the typical structure required for all implementations and the interfaces required to help the OSF/1 and OpenVMS working systems.
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T h e low two bits of Rb a r e ignored. R a a n d Rb m a y specify t h e s a m e register; t h e t a r g e t calculation u s i n g t h e old value is done before t h e n e w value is assigned. All J u m p instructions do identical operations. They only differ in h i n t s to possible branch-prediction logic. T h e displacement field of t h e instruction is u s e d to p a s s t h i s information. T h e four different "opcodes" set different bit p a t t e r n s in disp<15:14>, a n d t h e h i n t o p e r a n d sets disp<13:0>.
T h e floating-point register to be used is specified by t h e F a , Fb, a n d Fc fields all pointing to t h e s a m e floating-point register. If t h e F a , F b , a n d Fc fields do not all 3-12 Common Architecture (I) point to t h e s a m e floating-point register, t h e n it is U N P R E D I C T A B L E which register is used. 5 PALcode Instruction Format T h e Privileged Architecture L i b r a r y (PALcode) format is used to specify extended processor functions. It h a s t h e format shown in F i g u r e 3 - 6 .
T h e displacement is t r e a t e d as a signed longword offset. This m e a n s it is shifted left two bits (to a d d r e s s a longword boundary), sign-extended to 64 bits, a n d added to t h e u p d a t e d P C to form t h e t a r g e t v i r t u a l a d d r e s s . T h e conditional b r a n c h i n s t r u c t i o n s a r e PC-relative only. T h e 21-bit signed displacement gives a forward/backward b r a n c h distance of + / - 1M instructions. Instruction Descriptions (I) 4-17 T h e t e s t is on t h e signed q u a d w o r d i n t e g e r i n t e r p r e t a t i o n of t h e register contents; all 64 bits a r e tested.