By R. del Río, F. Medeiro, B. Pérez-Verdú, J. M. De la Rosa, Á Rodríguez-V´zquez (auth.)
CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: blunders research and functional Design begins with an instructional presentation of the basics of low-pass sigma-delta modulators, their purposes, and their most typical architectures. It then offers an exhaustive research of SC circuit mistakes with a twofold consequence. at the one hand, compact expressions are derived to aid layout plans and speedy top-down layout. at the different, specified behavioral types are awarded to help actual verification. This set of types permits the fashion designer to figure out the necessary standards for the several modulator development blocks and shape the foundation of a scientific layout method. The ebook is finished in next chapters with the certain presentation of 3 high-performance modulator ICs: the 1st are meant for DSL-like purposes, while the 3rd one is meant for automobile sensors.
CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: errors research and sensible Design includes hugely beneficial details that's based to offer the reader the required perception on find out how to layout SC sigma-delta modulators.
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Extra info for CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design
Local resonator feedbacks can be also included to set notches in NTF f . 11. Note that one of the integrators has a z –1 delay in the numerator, whereas the other does not. A slightly less effective resonator would be built if both integrators had a z – 1 delay, since zeros would be moved vertically from the 1 j0 point. 12. Note from Fig. 25b that a modulator equivalent to that in Fig. 21 is obtained if all bi coefficients are zero, except for b 1 . 47), whereas STF will implement an all-pole low-pass filter — STF z = b 1 e D z .
DR and ENOB versus OSR for different modulator orders ( L ) and resolutions of the internal quantizer ( B ). 3 Single-Loop 6' Architectures In the previous section, the operation principles and ideal performance of generic 6'Ms have been introduced. This section presents 6' topologies using a certain number of integrators and one quantizer, which are often referred to as single-loop 6'Ms, but single-stage or single-quantizer architectures may also apply. Their linear performance will be discussed, as well as aspects that are not covered by the additive white noise approximation —such as pattern noise, idle tones, or instabilities.
In practice, the implementation of the decimator may differ from its conceptual representation in Fig. 8: the position of the digital filter and the downsampler can be swapped; both are often implemented in a single block; stages with moderate downsampling ratios can be cascaded if OSR is large, etc. [Croc83] [Vaid90] [Nors97b]. 10 (b) 6'M architecture: (a) Basic scheme, (b) Corresponding linear model. in the A-to-D conversion. From now on, we will hence focus on this block — although keeping in mind that a 6' ADC is more than just its 6'M.