By Mehdi Dehbashi, Görschwin Fey
This publication describes automatic debugging methods for the insects and the faults which seem in several abstraction degrees of a process. The authors hire a transaction-based debug method of platforms on the transaction-level, saying the proper relation of transactions. the automatic debug process for layout insects reveals the capability fault applicants at RTL and gate-level of a circuit. Debug concepts for good judgment insects and synchronization insects are established, allowing readers to localize the main tough insects. Debug automation for electric faults (delay faults)finds the doubtless failing speedpaths in a circuit at gate-level. many of the debug methods defined in attaining excessive analysis accuracy and decrease the debugging time, shortening the IC improvement cycle and extending the productiveness of designers.
- Describes a unified framework for debug automation used at either pre-silicon and post-silicon stages;
- Provides methods for debug automation of a procedure at diverse degrees of abstraction, i.e., chip, gate-level, RTL and transaction level;
- Includes options for debug automation of layout insects and electric faults, in addition to an infrastructure to debug NoC-based multiprocessor SoCs.
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Extra info for Debug Automation from Pre-Silicon to Post-Silicon
SEQ specifies that in the current transaction, the slave address has one word difference with the previous transaction address for this slave. OTHER specifies that in the current transaction, the slave address is neither SAME nor SEQ. 2. m1; s2; Rd; / represents the end of a read transaction from master m1 to slave s2 with any address. The symbol “ ” indicates that we leave the address field as don’t care. As explained before, the tag field is not shown. The properties in terms of transaction sequences are defined at the temporal layer.
Different operators are available at this layer such as concatenation operator (;), fusion operator (:), or operator (|), and operator (&) and repetition operators 22 2 Preliminaries (*, C, D) [GF09]. The always operator means that the temporal expression has to hold at any time. The never operator means that the temporal expression has to never hold. The eventually operator means that the temporal expression has to hold at the current time or some future time [GF09]. Last layer in Fig. 9 is verification layer.
0; 1; 0; 0/. 18 2 Preliminaries The counterexample CE is given for debugging. Debugging finds the fault candidates according to the given counterexample. To debug the implementation, first the implementation is enhanced by correction blocks to create the debugging instance (Fig. 6b). One correction block is inserted at the output of each gate. The select lines of the correction blocks are controlled by the fault cardinality constraint. The debug instance is translated into CNF. A SAT solver is utilized to find and to enumerate all possible solutions (fault candidates).