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By Pierre-Emmanuel Gaillardon

This ebook discusses the possibilities provided by way of disruptive applied sciences to beat the good value and actual limits at present confronted through the electronics undefined. It presents a brand new method for the quick assessment of an rising know-how from an architectural potential and discusses the results from easy circuits to advanced architectures. a number of applied sciences are mentioned, starting from 3D integration of units (Phase switch thoughts, Monolithic 3-D, Vertical NanoWires-based transistors) to dense 2-D preparations (Double-Gate Carbon Nanotubes, Sublithographic Nanowires, Lithographic Crossbar arrangements). Novel architectural firms, in addition to the linked instruments, are provided which will discover this freshly opened layout space.

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Mead, Analog VLSI and Neural Systems (Addison Wesley, Menlo Park, 1989) 34. B. K. Likharev, Reconfigurable hybrid CMOS/nanodevice circuits for image processing. IEEE Trans. Nanotechnol. 6(6), 696–710 (2007) 35. W. -Y. L. Olynick, J. Straznicky, Z. Li, X. A. Ohlberg, Y. Y. A. M. S. Williams, One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography. Appl. Phys. A Mater. Sci. Process. 80(6), 1173–1178 (2005) 36. Y. P. O. A. Nielsen, E. DeIonno, G. Ho, J.

Shumarayev, Interconnect enhancements for a high-speed PLD architecture, in Proceedings of the ACM/SIGDA 10th International Symposium on FPGA (2002), p. 3 24. D. Lewis, E. Ahmed, G. Baeckler, V. Betz, M. Bourgeault, D. Cashman, D. Galloway, M. Hutton, C. Lane, A. Lee, P. Leventis, S. Marquardt, C. McClintock, K. Padalia, B. Pedersen, G. Powell, B. Ratchev, S. Reddy, J. Schleicher, K. Stevens, R. Yuan, R. Cliff, J. Rose, The Stratix II logic and routing architecture, in Abstracts of the ACM/SIGDA 13th International Symposium on.

It is then possible to optimize the logic fabric to the application, during the synthesis and packing operations. Within the CLB, extra circuitries have been added to address specific functionalities. We can point out in particular notice the carry lines, the SRAM decoders and the shift-register. 1 Conventional Reconfigurable Architecture Overview Fig. 8 Virtex-6 logic block [15] Fractionable 6-inputs LUTs 27 Flip-Flops 1 3 Extra-Logic 1-Fast carry look-ahead 2-Memory addressing 3-Shift Register 2 The carry lines extend through several LBs, in order to implement logic multipliers efficiently.

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