Download Functional Verification of Dynamically Reconfigurable by Lingkan Gong, Oliver Diessel PDF

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By Lingkan Gong, Oliver Diessel

This publication analyzes the demanding situations in verifying Dynamically Reconfigurable platforms (DRS) with recognize to the person layout and the actual implementation of such platforms. The authors describe using a simulation-only layer to emulate the habit of aim FPGAs and properly version the attribute positive factors of reconfiguration. Readers are enabled with this simulation-only layer to take care of verification productiveness by way of abstracting away the actual info of the FPGA textile. implementations of the simulation-only layer are incorporated: prolonged Re Channel is a process C library that may be used to ascertain DRS designs at a excessive point; ReSim is a library to help RTL simulation of a DRS reconfiguring either its good judgment and nation. via a couple of case reports, the authors show how their technique integrates seamlessly with latest, mainstream DRS layout flows and with well-established verification methodologies equivalent to top-down modeling and coverage-driven verification.

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Extra info for Functional Verification of Dynamically Reconfigurable FPGA-based Systems

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For the sake of verification productivity, it is desirable that functional verification is independent of the FPGA fabric. An ideal simulation method therefore needs to strike the right balance between the level of accuracy of the simulation and the level of detail of the fabric being modeled. Furthermore, this balance is constrained by the desire for the simulated design to be implementation ready (see Sect. 1). Thus, the design should not be changed for simulation purposes. The exact design that is used for implementation is simulated, tested and verified.

Numerical IDs of modules) that can be processed by the rest of the simulation-only layer. – Returns a readback SimB instead of readback bitstream when simulating configuration readback. • The part of configuration memory to which each RR is mapped is modeled by an RR artifact,3 which – Controls module swapping by selecting a MUX-like module_selector, which connects one and only one active RM to the static region. – Triggers module swapping according to the numerical IDs of modules. – Injects errors to the static region so as to mimic the spurious RM outputs during reconfiguration.

Property checking), or represent the same design at a higher level of abstraction (as done in equivalence checking) [24]. However, the execution times of formal methods do not scale well with design size. These methods are therefore only suitable for small designs [70]. Furthermore, there is no straightforward way of verfying the correctness or the completeness of the formal specification itself. In particular, a bug can be introduced to the formal specification or it may only capture a subset of the required design functionality.

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