By Stephan Eggersglüß, Rolf Drechsler
This ebook offers an summary of automated attempt trend new release (ATPG) and introduces novel suggestions to counterpoint classical ATPG, in accordance with Boolean Satisfiability (SAT). a quick and hugely fault effective SAT-based ATPG framework is gifted that's additionally in a position to generate fine quality hold up assessments resembling strong course hold up exams, in addition to exams with lengthy propagation paths to observe small hold up defects.
The objective of the ideas and methodologies awarded during this booklet is to enhance SAT-based ATPG, to be able to make it appropriate in commercial perform. Readers will discover ways to increase the functionality and robustness of the general try out new release approach, in order that the ATPG set of rules reliably will generate try out styles for many specific faults in appropriate run time to fulfill the excessive fault assurance calls for of undefined. The thoughts and enhancements awarded during this ebook give you the following advantages:
- Provides a accomplished creation to check iteration and Boolean Satisfiability (SAT);
- Describes a hugely fault effective SAT-based ATPG framework;
- Introduces circuit-oriented SAT fixing recommendations, which utilize structural info and may be able to speed up the quest approach significantly;
- Provides SAT formulations for the well-known hold up faults types, as well as the classical stuck-at fault model;
- Includes an business viewpoint at the cutting-edge within the checking out, in addition to SAT; issues in most cases individual from every one other.
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Additional resources for High Quality Test Pattern Generation and Boolean Satisfiability
The general flow in a test environment is given in Fig. 13. The flow can be divided roughly in the following three phases: netlist compilation, Design-For-Test (DFT) insertion and ATPG. The last one is described in more detail, because the techniques proposed in this book are applied in this phase. First, the design is read in the netlist compilation phase from a hardware description language and compiled into a netlist consisting of a set of primitive gate types (see for example the gate types given in Fig.
No Fault Simulation Primary Faults Remaining? No Test Set Fig. 15 ATPG phase – high compaction other test pattern. Additionally, the tests are merged. Multiple test patterns which all have non-conflicting input assignments can be merged into a single test pattern. The number of don’t care assignments should be generally as high as possible in order to achieve a good static compaction rate. A dynamic compaction scheme is applied in the high compaction stage (shown in Fig. 15).
When F1 dominates F2 and F2 dominates F1 as well, F1 and F2 are said to be equivalent. If F1 dominates F2 , a test has to be generated only for F2 . If F1 and F2 are equivalent, a test can be generated either for F1 or F2 to detect both faults. The procedure to reduce the target fault set by exploiting fault dominance relationships is called fault collapsing [ABF90]. 20 Fig. 7 Fault collapsing. (a) Uncollapsed fault set and (b) collapsed fault set 2 Circuits and Testing a (a,0) (a,1) (c,0) (c,1) (b,0) (b,1) b (a,1) (c,1) (b,1) Usually, fault equivalence and fault dominance relationships are exploited only locally since the overhead for identifying all relationships is too high [Lio92].