Download The Architecture of High Performance Computers by Roland N. Ibbett (auth.) PDF

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By Roland N. Ibbett (auth.)

Introduction 1. 1 historic advancements 1 1. 2 recommendations for making improvements to functionality 2 1. three An Architectural layout instance three 2 directions and Addresses 2. 1 Three-address platforms - The CDC 6600 and 7600 7 2. 2 Two-address platforms - The IBM System/360 and /370 10 2. three One-address structures 12 2. four Zero-address platforms 15 2. five The MU5 guideline Set 17 2. 6 evaluating guide codecs 22 three garage Hierarcbies three. 1 shop Interleaving 26 three. 2 The Atlas Paging process 29 three. three IBM Cache structures 33 three. four The MU5 identify shop 37 three. five facts Transfers within the MU5 garage Hierarchy forty four four Pipelines four. 1 The MU5 fundamental Operand Unit Pipeline forty nine four. 2 mathematics Pipelines - The TI ASC sixty two four. three The IBM System/360 version ninety one universal info Bus sixty seven five guideline Buffering five. 1 The IBM System/360 version 195 guide Processor seventy two five. 2 guide Buffering in CDC desktops seventy seven five. three The MU5 guide Buffer Unit eighty two five. four The CRAY-1 guide Buffers 87 five. five place of the keep watch over aspect 89 6 Parallel sensible devices 6. 1 The CDC 6600 imperative Processor ninety five 6. 2 The CDC 7600 imperative Processor 104 6. three functionality a hundred and ten 6 • four The CRA Y-1 112 7 Vector Processors 7. 1 Vector amenities in MU5 126 7. 2 String Operations in MU5 136 7. three The CDC Star-100 142 7. four The CDC CYBER 205 146 7.

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5). As a result there are some ten pipeline stages between the end of PROP and the A-unit through which all instruetions destined for the A-uni t must pass (in order to maintain the correct program sequence). Thus i f a name held in the PROP Name Store were to be used to accumulate a total ealeulated by ACC orders in a small program loop, the order reading the total from the Name Store would have to be held up until the value calculated by the previous pass through the loop had been returned. The solution to this problem was the provision of 24 lines of Name Store in OBS.

The time for a floating-point addition in Mercury, for example, was 180 US, while the co re store cycle time was 10 US. 6 US, while the co re store cycle time was 2 uso Thus, in the absence of some special technique, the time required to access both an instruction and its operand would have amounted to 4 us, leaving the floating-point unit idle for much of its time. Part of the solution to this problem was to overlap arithmetic and store accessing operations for successive instructions, a development which we shall consider in more detail in Chapter 4.

A full virtual address in MU5 consists of a 4-bit Process Number, a 14-bit Segment Number and 16 bits which identify a 32-bit word within a segment. Addresses presented to the Name Store do not contain the Segment Number, however, since it was assumed at the design stage that the Name Segment would always be zero, and only 15 of the word address bits are 38 The Architecture of High Performance Computers used, referring to 64-bit operands. Where necessary, a 32-bit operand is selected from within a 64-bit word in a later stage of the pipeline.

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